DON'T MISS THE BUS
GO ROUTE 1 TO HIGH SPEED DIGITAL DESIGN SUCCESS
DON'T MISS THE BUS
GO ROUTE 1 TO HIGH SPEED DIGITAL DESIGN SUCCESS
LIVE WEBINAR
LIVE WEBINAR
19th January 2:30PM
Presented by
Steve Gascoigne
Senior App Eng. Consultant
PCB & Analysis Solutions
From Siemens Digital Industries Software
19th January 2:30 PM
Presented by
Steve Gascoigne
Senior App Eng. Consultant
PCB & Analysis Solutions
From Siemens Digital Industries Software
Building with High Speed Interfaces : Solving PCB Design Challenges
The Smaller, denser, faster mantra has never been truer in Modern Electronic design.
Analysing and verifying serial channels for compliance with over 200 different protocols and variants is challenge for any engineer or design. These challenges result in complex designs and increase the essential need to simulate and validate your design before wasting money, time and effort with prototype failures.
Register for our webinar and discover how engineers are meeting and beating these challenges.
Topics covered include:-
- SERDES channel analysis and design requires electromagnetic (EM) expertise. Some design teams do not have SI or EM experts in house, so the additional burden of generating S-parameter models that accurately represent the PCB design is borne by the hardware design engineer.
- SERDES specifications are written by compliance bodies and are inconsistent across protocols. For example, jitter is specified in a different way in the PCI Express and IBIS-AMI specifications.
- Multiple SERDES protocols exist in the same printed circuit board (PCB) design. With little knowledge transfer between protocols, interconnect analysis has to start from scratch for every protocol.
- With shrinking design cycles, hardware engineers do not have the time to read sometimes obscurely written specifications.
- SERDES specifications are not free or easily accessible.
- SERDES channel analysis and design requires electromagnetic (EM) expertise. Some design teams do not have SI or EM experts in house, so the additional burden of generating S-parameter models that accurately represent the PCB design is borne by the hardware design engineer.
- SERDES specifications are written by compliance bodies and are inconsistent across protocols. For example, jitter is specified in a different way in the PCI Express and IBIS-AMI specifications.
- Multiple SERDES protocols exist in the same printed circuit board (PCB) design. With little knowledge transfer between protocols, interconnect analysis has to start from scratch for every protocol.
- With shrinking design cycles, hardware engineers do not have the time to read sometimes obscurely written specifications.
- SERDES specifications are not free or easily accessible.